1. Field of the Invention
The present invention generally relates to a data transfer device and a data transfer method.
2. Description of the Related Art
Conventionally, a technique of separating phases of command and data and first sending a command in the phase of command has been researched as in Japanese Unexamined Patent Application Publication No. 2005-1518127. In case where a data transfer device includes a plurality of direct memory access controllers (DMACs) having functions as in the Japanese Unexamined Patent Application Publication No. 2005-1518127, and sends data to and receives data from a dynamic random access memory controller (DRAMC) through an arbitration by an arbiter, when if a certain DMAC causes a failure there is a need for resetting only the DMAC having the failure instead of resetting the entire data transfer device.
Meanwhile, in Japanese Unexamined Patent Application Publication No. Hei. 5-151156, there is disclosed a conventional technique of stopping an operation after completion of arbitration or a selection and preventing a stop while a connection with the other party is bad.
However, there is a problem that a data transfer in a data transfer device cannot be continued in its entirety even though a DMAC, which first sends a command as in the Japanese Unexamined Patent Application Publication No. 2005-1518127, is controlled to prevent a reset as in Japanese Unexamined Patent Application Publication No. Hei. 5-151156.
Hereinafter, the problem will be explained. First, an example of timing chart of “READ” between a DMAC first sending a command and an arbiter will be explained. FIG. 1 shows an example of a timing chart between a DMAC and an arbiter.
A DRAMC asserts a command acknowledgement (com_ack) through the arbiter upon receipt of a command request (com_req) by the DMAC. Next, the DRAMC outputs a read data to the DMAC through the arbiter, and the DMAC receives the read data by asserting a data acknowledgement (data_ack).
Next, an example of timing chart in “READ” between the arbiter and the DRAMC. FIG. 2 shows an example of timing chart between the arbiter and the DRAMC. The arbiter issues a command to the DRAMC after allocating tags to respective DMACs in order for identifying which DMAC it is. Next, the DRAMC returns one of the tags to the arbiter in a data phase, and the arbiter allocates the read data to the DMAC in reference to one of the tags.
Next, a timing chart of the above problem will be explained. FIG. 3 shows an example of a timing chart of a discontinuous data transfer. When a reset is requested after the DMAC issues the command, the DMAC thus reset cannot respond to a request in a data phase from the DRAMC, thereby causing a problem that the DRAMC is waiting for response. State differently, when a DRAM which has issued a command in a duration between a command phase and a data phase is reset, the data transfer device falls into a state in which overall data transfers cannot be continue.